(1) Field of the Invention
The present invention relates generally to capacitors in semiconductor memory devices and more particularly to a method of manufacturing a high capacitance storage electrode for ULSI DRAMs.
(2) Description of the Related Art
In the ultra large scale integrated (ULSI) technology of today, the ultra scaling down of the physical area of circuitry on a semiconductor substrate has placed a greater technological demand on the dynamic random access memory (DRAM) devices. This is because, as the areas occupied by the memory cells have been scaled down over the years, the minimum amount of stored charge needed to maintain reliable memory operation has remained the same. And yet, the capacitance is directly proportional to the area of the capacitor. This constant charge-storage value has to be maintained for future DRAM generations as well even as the cell sizes shrink even further.
As is well known in the art, the storage capacity of capacitors in memory cells can be increased by making the capacitor dielectric thinner, by using an insulator with a larger dielectric constant, or by increasing the area of the capacitor. The third option of increasing the capacitor area can be effective and has been exploited in certain different ways. One way is to form three-dimensional structures in place of planar capacitors. In this approach, the storage capacitor is formed in a trench etched in a semiconductor substrate. The silicon-area reduction of a trench capacitor compared to a planar capacitor can be a factor of eighteen or more, for example. Alternatively, the storage capacitor of a cell can be formed, or stacked, on top of its access transistor, thereby shrinking the cell size without a loss of its storage capacity. In still another approach, a three-dimensional tree-like effect can be realized by forming a finned structure with leaves extending from the same capacitor trunk. Many variations of such three-dimensional capacitors are reported in prior art.
General usage of trench structures are well known in isolation technology where they are used to isolate devices in integrated circuits. There are differences in these structures, however, when they are used for DRAM capacitors, in particular. As stated earlier, storage capacity is inversely proportional to the dielectric thickness, and therefore, in the case of a trench capacitor, the dielectric film on the walls of the trench must be much thinner than on the walls of an isolation trench. Also, since polysilicon is usually used as the filler material in the trench, and since in the case of a trench capacitor this material also serves as one plate of the capacitor, it must consist of highly doped polysilicon. Usually the semiconductor on the other side of the thin dielectric serves as the other capacitor plate. The role of the polysilicon inside the trench as the storage electrode or plate electrode will vary depending upon the particular design used.
Similar considerations as in trench-capacitors apply when three-dimensional capacitors are formed above the access transistors on a semiconductor substrate. In prior art, some of these structures are referred to as stacked capacitors (STCs). As usual, the properties of the dielectric, and the area of the capacitor play a significant role in determining the storage capacity. Thus, for STC cells to be made feasible for high-density DRAMs of 64 Mega-bit and beyond, an insulator with a larger dielectric constant than that of SiO.sub.2 must be made available, or novel structures must be developed. In the absence of the former presently, several novel STC cells have been reported in the literature.
A very recent STC is a three-dimensional finned structure forming a tree-like capacitor which is shown in FIG. 1. Different methods of manufacturing essentially the same structure are disclosed in various patents. A conventional method of forming such a capacitor follows the steps described by Lur, for example, in U.S. Pat. No. 5,604,148. Following Lur, but without going into unnecessary details so as to not obscure the main features of forming three-dimensional capacitors, it is sufficient to note in FIG. 1 the tree-like structure (38) and its formation as follows: first, an active region in a semiconductor substrate (10) is isolated from other active regions by forming field oxide regions (20) using commonly practiced isolation methods such as LOCOS (local oxidation of silicon). Subsequently, transistors having a source(30) and drain (40) regions, and a gate electrode (25) and commonly shared bit line (45) are formed in the active region using again common semiconductor manufacturing methods such as deposition, photolithography, and ion-implantation.
The structure so formed is then conformally deposited with a first insulating layer (50), and then followed by a second insulating layer including upper (not shown) and lower insulating layers where the lower layer (70) is an etch-blocking layer (70), such as silicon nitride (Si.sub.3 N.sub.4). In FIG. 1, an intermediate insulating layer (60) is also shown which is sometimes used for planarizing the underlying layer. A contact hole is next formed over the source region (30) and filled with a conductive material forming a metal trunk (31). The upper layer of the second insulating layer surrounding trunk (31) is then removed and the space around the metal trunk is filled with alternating rings of conductive material (33) and insulating material (35) such that when a metal cap (37) is formed in mating disposition with the metal ring layers, a three-dimensional tree-shaped lower electrode (38) is formed as shown in FIG. 1. Finally, upper electrode (80) is formed after depositing a thin layer of dielectric (39) over the surface of the lower electrode comprising metal parts (31) and (37), thus forming a capacitor.
Another method of forming capacitors with increased electrode surface is taught by Rha in U.S. Pat. No. 5,387,531. In this approach, after the forming of a MOS transistor, three different layers are deposited in the order of an in-situ doped non-crystalline silicon, an undoped non-crystalline silicon, and a hemispherical polysilicon. An upper oxide film is next deposited, and then, etched back so that the hemispherical polysilicon domes are exposed. Using the remained portions of the upper oxide film remaining in the valleys of hemispherical polysilicon as a mask, the polysilicon is etched to form a plurality of holes perforated from the domes to the underlying insulating layer. Thus, the polysilicon layer with the holes, and hence with increased area, become the lower electrode of a stack capacitor. The upper electrode is formed after coating the lower electrode with a high dielectric layer such as oxynitride ONO, and depositing a conducting material.
In U.S. Pat. No. 5,336,630, Yun describes a different method of making a semiconductor memory device where the storage node having a plurality of pillars is capable of increasing the storage node surface area and thus the cell capacitance. This method, which utilizes a direct electron beam patterning of a photoresist layer is simpler than the previously cited prior art methods. A still simpler method is proposed in this invention where larger gain can be achieved in increasing the area of the storage electrode of a memory device by employing a microphotolithographic patterning technique as disclosed below in the embodiment of this invention.